Compartir
Logic Design And Verification Using Systemverilog (revised) (en Inglés)
Donald Thomas
(Autor)
·
Createspace Independent Publishing Platform
· Tapa Blanda
Logic Design And Verification Using Systemverilog (revised) (en Inglés) - Thomas, Donald
79,59 €
83,78 €
Ahorras: 4,19 €
Elige la lista en la que quieres agregar tu producto o crea una nueva lista
✓ Producto agregado correctamente a la lista de deseos.
Ir a Mis Listas
Origen: Estados Unidos
(Costos de importación incluídos en el precio)
Se enviará desde nuestra bodega entre el
Viernes 14 de Junio y el
Miércoles 03 de Julio.
Lo recibirás en cualquier lugar de España entre 1 y 5 días hábiles luego del envío.
Reseña del libro "Logic Design And Verification Using Systemverilog (revised) (en Inglés)"
SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: -students currently in an introductory logic design course that also teaches SystemVerilog, -designers who want to update their skills from Verilog or VHDL, and -students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design - these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book's topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
Todos los libros de nuestro catálogo son Originales.
El libro está escrito en Inglés.
La encuadernación de esta edición es Tapa Blanda.
✓ Producto agregado correctamente al carro, Ir a Pagar.
