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generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring (en Inglés)
Marc Boulé
(Autor)
·
Zeljko Zilic
(Autor)
·
Springer
· Tapa Blanda
generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring (en Inglés) - Boulé, Marc ; Zilic, Zeljko
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Origen: Estados Unidos
(Costos de importación incluídos en el precio)
Se enviará desde nuestra bodega entre el
Lunes 17 de Junio y el
Jueves 04 de Julio.
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Reseña del libro "generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring (en Inglés)"
Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an "under-the-hood" view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.
